In order to read a stored state of a memory cell in a semiconductor storage device, various kinds of methods have been employed. As an example, a flash memory that is a nonvolatile semiconductor storage device will be described. The flash memory comprises a memory transistor in which each memory cell has a floating gate structure, and information is stored according to an amount of electric charge (electrons) injected to the floating gate of each memory cell. More specifically, in a state many electrons are injected in the floating gate, an inversion layer is not likely to be formed in a channel region, so that a threshold voltage of the memory cell becomes high (defined as a programmed state). Meanwhile, in a state the electrons are discharged from the floating gate, the inversion layer is likely to be formed in the channel region, so that the threshold voltage of the memory cell becomes low (defined as an erased state). In order to determine whether the selected memory cell is in the programmed state or the erased state at high speed, a reference memory cell having a threshold voltage intermediate between the programmed state and the erased state is prepared and inputted to a differential input type of sense amplifier circuit.
Here, as shown in FIG. 8, in a semiconductor storage device having a memory plane in which memory blocks having the above described hierarchic bit line structure are arranged in a column direction, when a memory cell to be read (selected memory cell schematically shown by ◯ in FIG. 8) is selected from the memory block in the memory plane and its stored data is read by a differential input type of sense amplifier circuit provided adjacent to the memory plane, the selected memory cell is connected to one of two input terminals of the sense amplifier circuit through a selection bit line connected to the selected memory cell in the memory block and a global bit line connected to the selection bit line, and a reference memory cell (schematically shown by ● in FIG. 8) is connected to the other of the input terminals. The stored state (threshold voltage in the case of a flash memory) of the reference memory cell is set so as to have a memory cell current intermediate between the memory cell currents varying depending on the stored state of the selected memory cell.
Furthermore, when load capacity of the two input terminals of the sense amplifier circuit is not equal, a difference in transient current for charging the load capacity is generated in a transient state in which each memory cell current is supplied to the selected memory cell and the reference memory cell through the two input terminals, so that a current difference between the selected memory cell current and the reference memory cell current is not correctly generated as a voltage difference between the two input terminals of the sense amplifier circuit. Since this problem hinders the high-speed reading operation, in order to improve the transient response characteristics at the time of the reading operation, load capacity that is parasitic in the global bit line connected to the two input terminals of the sense amplifier is to be equalized.
For example, as shown in FIG. 3, in a nonvolatile semiconductor storage device disclosed in the following Patent Document 1, another global bit line that is not connected to the selected memory cell (referred to as a “dummy global bit line” occasionally hereinafter) is connected to one input terminal of the sense amplifier circuit for the reference memory cell, one bit line (referred to as a “dummy bit line” occasionally hereinafter) in the memory block (referred to as a “dummy block” occasionally hereinafter) that does not contain the selected memory cell is selected and connected to the dummy global bit line, whereby the load capacity that is parasitic in the global bit lines connected to the two input terminals of the sense amplifier circuit is equalized. According to the above constitution, parasitic capacity of one global bit line and parasitic capacity of one bit line are equally added to each input terminal of the sense amplifier circuit, so that the load capacity can be equalized as a whole. In addition, as the dummy block, the memory block adjacent to the memory block selected in view of the parasitic resistance in the global bit line is selected according to a certain rule in general. FIG. 3 is a schematic circuit diagram showing the memory plane structure shown in FIG. 8 in more detail, and it schematically shows that the selected memory cell and the dummy bit line are selected. In addition, broken lines designate unselected state or inactivated state.    Patent Document 1: Japanese unexamined Patent Publication No. 2003-77282